The present invention relates to a variable length coding method and a variable length coding apparatus and, more particularly, to a variable length coding method and a variable length coding apparatus for realizing variable length coding according to MPEG4 and H.263 as standards of the picture coding system.
As examples of the system for coding or decoding moving picture data using band compression technology, there are an MPEG (Moving Picture Coding Experts Group) system that is standardized by the ISO, an H.263 system that is recommended by the ITU-T and the like. Basically in these systems, a screen is divided into blocks, each of which is composed of plural pixels, with utilizing correlation within the screen, then DCT (Discrete Cosine Transform) as one of the orthogonal transform system is performed on data in this block, and respective processes of quantization and VLC (variable Length Code) are carried out, thereby compressing the picture data.
In this VLC process, with respect to DCT coefficients obtained as a result of the DCT, Run which is the number of preceding coefficients of zero, Level which is a value of a non-zero coefficient and Last indicating whether the non-zero coefficient is the last one or not are taken as a combination of (Last, Run, Level), and a unique code is assigned thereto, thereby performing coding.
In MPEG4, a VLC table for the assignment of unique codes is defined, while three escape modes are applied to conform to cases where VLCs are not defined in this VLC table. In the first escape mode, with respect to the combination of (Last, Run, Level), LMAX which is the maximum Level value corresponding to Last and Run in the VLC table is subtracted from the absolute value of Level, and thereafter the VLC is performed again on the obtained result using the VLC table. In the second escape mode, with respect to the combination of (Last, Run, Level), a value which is obtained by adding 1 and RMAX as the maximum Run value corresponding Last and Level in the VLC table is subtracted from the value of Run, and thereafter the VLC is performed again on the obtained result using the VLC table. In the third escape mode, the above-mentioned combination is converted into a FLC (Fixed Length Code).
In the H.263 system and the like, the VLC table for assignment of unique codes is defined as in MPEG4, while the escape mode is only a mode of converting a combination into a FLC.
Hereinafter, a prior art process chart of the VLC in the MPEG4 will be described with reference to FIG. 12.
Initially, the description will be given of a variable length coding method by which, from the DCT coefficients rearranged in an one-dimensional array, Run as the number of preceding zero coefficients, Level as a non-zero coefficient value, and Last indicating whether the non-zero coefficient is the last one are taken as a combination of (Last, Run, Level), then a VLC process is carried out for assigning a unique code to the combination, and when the VLC assignment cannot be performed, three escape modes are applied.
FIG. 12 is a chart diagram for explaining the conventional variable length coding method.
In FIG. 12, ◯ (white circle) means that data is determined, and numerals 01 to 09 denote process steps for respective coefficients. Further, Coding B corresponds to the first escape mode, Coding C corresponds to the second escape mode, and Coding D corresponds to the third escape mode.
Hereinafter, the process steps for respective coefficients are described.
In Coding A, the process 01 is a process that is activated by Last, Run and Level (i.e., the tact that there are all data at the input/output time), and when a code corresponding to the combination of (Last, Run, Level) exists in a VLC table, Code1 is outputted to the process 09, thereby completing the process. On the other hand, when the code corresponding to the combination of (Last, Run, Level) does not exist in the VLC table, a code indicating xe2x80x9cNot existxe2x80x9d is outputted to Coding B.
In the Coding B, the process 02 is a process that is activated by Last and Run in the case where the corresponding code does not exist in the VLC table in the process 01, and LMAX as the maximum Level value corresponding to the combination of (Last, Run) is outputted to process 03.
The process 03 is a process that is activated by LMAX, and a process of subtracting LMAX from the Level value is carried out and a resulting NewLevel value to process 04 is outputted.
The process 04 is a process that is activated by Last, Run and Newlevel, and when a code corresponding to the combination of (Last, Run, Newlevel) exists in a VLC table, a Code2 is outputted to the process 09, thereby completing the process. On the other hand, when the code corresponding to the combination of (Last, Run, Newlevel) does not exist in the VLC table, a code indicating xe2x80x9cNot existxe2x80x9d is outputted to Coding C.
In the Coding C, the process 05 is a process that is activated by Last and Level in the case where the corresponding code does not exist in the VLC table in the process 04, and RMAX as the maximum Run value corresponding to the combination of (Last, Level) is outputted to the process 06.
The process 06 is a process that is activated by RMAX, and a process of subtracting the sum of RMAX and 1 from the Run value is carried out and a resulting NewRun value is outputted to the process 07.
The process 07 is a process that is activated by Last, NewRun and Level, and when a code corresponding to the combination of (Last, NewRun, Level) exists in a VLC table, a Code 3 is outputted to the process 09, thereby completing the process. On the other hand, when the code corresponding to the combination of (Last, NewRun, Level) does not exist in the VLC table, a code indicating xe2x80x9cNot existxe2x80x9d is outputted to Coding D.
In the Coding D, the process 08 is a process of converting Last, Run and Level by FLC in the case where the corresponding code does not exist in the VLC table in the process 07, and a Code4 as a FLC is outputted to the process 09.
In the process 09, an effective code is activated among the Code1-Code4 and the activated code is outputted.
FIG. 13 is a diagram summarizing processing contents of each cycle of the prior art variable length coding method.
Hereinafter, the operation of each cycle will be described. Here, the process contents in the figure are shown inside parentheses.
Initially, in the first cycle (1T), a process as normal VLC that is activated by Last, Run and Level is carried out (NORMAL VLC), and a judgement as to whether the result of the normal VLC exists in the table is made (NORMAL VLC judgement).
In the second cycle (2T), when the result of the normal VLC exists in the table in the 1T process, the result is outputted (VLC result). on the other hand, when the result of the normal VLC does not exist in the table, LMAX as the maximum Level value corresponding to Last and Run is subtracted from the Level value, thereby obtaining a NewLevel value (LMAX).
The third cycle (3T) is a process that is activated by LMAX, in which VLC corresponding to the combination of Last, Run and NewLevel is carried out (LMAX VLC). Then, a judgement as to whether the result of the VLC corresponding to the combination of Last, Run and NewLevel exists in the table is made (LMAX VLC judgement).
In the fourth cycle (4T), when the LMAX VLC result exists in the table in the 3T process, the result is outputted (VLC result). On the other hand, when the LMAX VLC result does not exist in the table, a value which is obtained by adding RMAX as the maximum Run value corresponding to Last and Level and 1 is subtracted from the Run value, thereby obtaining a NewRun value (RMAX).
The fifth cycle (5T) is a process that is activating by RMAX, in which VLC corresponding to the combination of Last, NewRun and Level is carried out (RMAX VLC). Then, a judgement as to whether the result of the VLC corresponding to the combination of Last, NewRun and Level exists in the table is made (RMAX VLC judgement).
In the sixth cycle (6T), when the RMAX VLC result exists in the table in the 5T process, the result is outputted (VLC result). On the other hand, when the RMAX VLC result does not exists in the table, Last, Run and Level are processed with a FLC, and the result is outputted (FLC result).
However, in the prior art VLC process chart according to MPEG4, assuming the process of referring to each table to be one cycle, six cycles of processing (6T) are required until the FLC result is outputted. When one FLC exists in one block, it means that there are six FLCs in one macroblock. Therefore, for one FLC, the FLC process requires 36 cycles at the maximum. To be more specific, as the number of blocks is increased, the number of cycles is increased, whereby the process speed is decreased.
The present invention is made to solve these problems, and has for its object to provide a variable length coding method and a variable length coding apparatus, which can reduces the number of arithmetic cycles and efficiently carries out VLC processes.
According to the present invention (aspect 1), there is provided a variable length coding method by which Run as the number of preceding zero coefficients, Level as a value of a non-zero coefficient, and Last indicating whether the non-zero coefficient is the last one are taken from discrete cosine transform coefficients which are rearranged in an one-dimensional array as a combination of (Last, Run, Level) , a VLC process of assigning a unique code to the combination is carried out, and when the VLC assignment cannot be performed, three escape modes are applied, thereby performing coding, in which processes of: step (a) of performing the code assignment for the combination of (Last, Run, Level); step (b), as a first escape mode, of subtracting LMAX as a maximum Level corresponding to (Last, Run) from Level, and performing code assignment for a combination including an obtained amended Level of (Last, Run, amended Level); step (c), as a second escape mode, of subtracting a value that is obtained by adding RMAX as a maximum Run corresponding to (Last, Level) and 1 from Run, and performing code assignment for a combination including an obtained amended Run of (Last, amended Run, Level); and step (d), as a third escape mode, of assigning a FLC are carried out in parallel with each other, and step (e) of selecting the codes assigned in the steps (a) to (d) in the order of priorities: (a), (b), (c), (d), and outputting the selected codes is carried out.
According to the present invention (aspect 2), in the variable length coding method of aspect 1, according to a method for assigning the variable length code, the order of priorities by which coded data is selected in the step (e) is decided by selecting one of three patterns: (a), (b), (c), (d); (a), (c), (b), (d); and (a), (d).
According to the variable length coding method that is constructed as described above, the priorities can be arbitrarily set, and further a unique code is always assigned by the FLC in step (d). Therefore, when the order of priorities are determined as step (a), step (d) (steps (b) and (c) are not in order), it can be forcefully decided not to select steps (b) and (c), whereby this method can conform to H.263 that is an image compression method by which the variable length coding is performed in step (a) and (d).
According to the present invention (aspect 3), there is provided a variable length coding apparatus comprising an RMAX table for receiving a Level absolute value signal as an absolute value of a Level signal and a Last signal; an LMAX table for receiving a Run signal and the Last signal; a first VLC table for receiving the Level absolute value signal, a signal indicating the sign of the Level signal, the Run signal, and the Last signal; a first subtraction circuit for subtracting a sum of an output signal of the RMAX table and 1, from the Run signal; a second register for holding an output signal of the first subtraction circuit; a second VLC table for receiving an output signal of the second register, the Level absolute value signal, the signal indicating the sign of the Level signal, and the Last signal; a second subtraction circuit for subtracting an output signal of the LMAX table from the Level absolute value signal; a third register for holding an output signal of the second subtraction circuit; a third VLC table for receiving an output signal of the third register, the signal indicating the sign of the Level signal, the Run signal, and the Last signal; a first register for holding an output signal of the first VLC table; a fourth register for holding an output signal of the second VLC table; a fifth register for holding an output signal of the third VLC table; an RMAX VLC generation circuit for receiving an output signal of the fourth register; an LMAX VLC generation circuit for receiving an output signal of the fifth register; a FLC generation circuit for receiving the Level signal, the Run signal, and the Last signal; a control circuit for receiving an output signal of the first register, the output signal of the fourth register, and the output signal of the fifth register; and a selection circuit for receiving the output signal of the first register, an output signal of the RMAX VLC generation circuit, an output signal of the LMAX VLC generation circuit, and an output signal of the FLC generation circuit, in which the control circuit judges whether the output signal of the first register, the output signal of the fourth register, and the output signal of the fifth register are correct as VLC, and outputs a selection signal for indicating the judgement result to the selection circuit, and the selection circuit selects one output signal from the output signal of the first register, the output signal of the PMAX VLC generation circuit, the output signal of the LMAX VLC generation circuit, and the output signal of the FLC generation circuit, in accordance with the selection signal, and outputs the selected signal as a code.
According to the variable length coding apparatus that is constituted as described above, all processes can be implemented in two cycles, whereby the number of the process cycles can be reduced.
According to the present invention (aspect 4), in the variable length coding apparatus of aspect 3, the control circuit judges whether the output signal of the first register, the output signal of the fourth register, and the output signal of the fifth register are correct as VLC, and outputs the judgement result to the selection circuit according to preset priorities.
According to the variable length coding apparatus that is constituted as described above, all processes can be implemented in two cycles, whereby the number of the process cycles can be reduced.
According to the present invention (aspect 5), there is provided a variable length coding apparatus comprising an PMAX table for receiving a Level absolute value signal as an absolute value of a Level signal and a Last signal; an LMAX table for receiving a Run signal and the Last signal; a first subtraction circuit for subtracting a sum of an output signal of the RMAX table and 1, from the Run signal; a second subtraction circuit for subtracting an output signal of the LMAX table from the Level absolute value signal; a second register for holding an output signal of the first subtraction circuit; a third register for holding an output signal of the second subtraction circuit; a first selection circuit for selecting one of an output signal of the third register and the Level absolute value signal; a second selection circuit for selecting one of an output signal of the second register and the Run signal; a VLC table for receiving an output signal of the first selection circuit, an output signal of the second selection circuit, a signal indicating the sign of the Level signal, and the Last signal; a first register for holding an output signal of the VLC table, a FLC generation circuit for receiving the Level signal, the Run signal, and the Last signal; a control circuit for receiving an output signal of the first register; a VLC generation circuit for receiving the output signal of the first register, and an output signal of the control circuit; and a third selection circuit for receiving an output signal of the VLC generation circuit and an output signal of the FLC generation circuit, in which in a first cycle, the first selection circuit receives a first selection signal outputted from the control circuit, selects the Level absolute value signal, and outputs the Level absolute value signal to the VLC table, the second selection circuit receives a second selection signal outputted from the control circuit, selects the Run signal, and outputs the Run signal to the VLC table, then the VLC table implements VLC, outputs an output signal to the first register, and in a second cycle, the control circuit judges whether the output signal of the first register is correct as normal VLC, and when the output signal of the first register is judged to be correct as normal VLC, outputs a third selection signal indicating the judgement result to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as a normal VLC code, and the third selection circuit selects the output signal of the VLC generation circuit in accordance with the third selection signal and outputs the selected signal, in the first cycle, the LMAX table receives the Last signal and the Run signal, generates an LMAX data signal, and outputs the LMAX data signal to the second subtraction circuit, the second subtraction circuit receives the LMAX data signal and the Level absolute value signal, subtracts the LMAX data signal from the Level absolute value signal, and outputs an obtained result to the third register, and in the second cycle, the first selection circuit receives the first selection signal outputted from the control circuit, selects the output signal of the third register, and outputs the selected signal to the VLC table, the second selection circuit receives the second selection signal outputted from the control circuit, selects the Run signal, and outputs the selected Run signal to the VLC table, then the VLC table implements VLC, outputs an output signal to the first register, and in the third cycle, when the judgement of the normal VLC performed in the second cycle shows that the output signal is not correct, the control circuit judges whether the output signal of the first register is correct as LMAX VLC, and when the output signal of the first register is judged to be correct as LMAX VLC, outputs the third selection signal indicating the judgement result to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as an LMAX VLC code, and the third selection circuit selects the output signal of the VLC generation circuit in accordance with the third selection signal and outputs the selected signal, and in the first cycle, the RMAX table receives the Last signal and the Level absolute value signal, generates an RMAX data signal, and outputs the RMAX data signal to the first subtraction circuit, the first subtraction circuit receives the RMAX data signal and the Run signal, subtracts a value that is obtained by adding the RMAX data signal and 1, from the Run signal, and outputs an obtained result to the second register, and in the third cycle, the first selection circuit receives the first selection signal outputted from the control circuit, selects the Level absolute value signal, and outputs the selected signal to the VLC table, the second selection circuit receives the second selection signal outputted from the control circuit, selects the output signal of the second register, and outputs the selected signal to the VLC table, then the VLC table implements VLC, outputs an output signal to the first register, and in a fourth cycle, when the judgement of the LMAX VLC performed in the third cycle shows that the output signal is not correct, the control circuit judges whether the output signal of the first register is correct as RMAX VLC, and when the output signal of the first register is judged to be correct as RMAX VLC, outputs the third selection signal to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as an RMAX VLC code, and the third selection circuit selects the output signal of the VLC generation circuit in accordance with the third selection signal and outputs the selected signal, and when it is judged that none of the output signals of the first register, inputted to the control circuit, is correct as VLC, in a fifth cycle, the third selection circuit selects the output signal of the FLC generation circuit and outputs the selected signal.
According to the variable length coding apparatus that is constituted as described above, the priorities can be arbitrarily set. Further, when the priorities are set so as to select the output signal of the first register and then the output signal of the FLC generation circuit (remaining two signals are not in order), this apparatus can conform to the image compression method according to H.263.
According to the variable length coding apparatus that is constituted as described above, the NewLevel signal and the NewRun signal can be calculated while simultaneously performing the normal VLC. Further, although the prior art VLC process requires six cycles, this apparatus can reduce the number of process cycles to five cycles. Furthermore, the process is conventionally carried out using three VLC tables, while this apparatus can perform the VLC with one VLC table, thereby reducing the circuit area.
According to the present invention (aspect 6), there is provided a variable length coding apparatus comprising an PMAX table for receiving a Level absolute value signal as an absolute value of a Level signal and a Last signal; an LMAX table for receiving a Run signal and the Last signal; a first subtraction circuit for subtracting a sum of an output signal of the PMAX table and 1, from the Run signal; a second subtraction circuit for subtracting an output signal of the LMAX table from the Level absolute value signal; a second register for holding an output signal of the first subtraction circuit; a third register for holding an output signal of the second subtraction circuit; a first selection circuit for selecting one of an output signal of the third register and the Level absolute value signal; a second selection circuit for selecting one of an output signal of the second register and the Run signal; a VLC table for receiving an output signal of the first selection circuit, and output signal of the second selection circuit, a signal indicating the sign of the Level signal, and the Last signal; a first register for holding an output signal of the VLC table; a FLC generation circuit for receiving the Level signal, the Run signal, and the Last signal; a control circuit for receiving an output signal of the first register; a VLC generation circuit for receiving the output signal of the first register and an output signal of the control circuit; and a third selection circuit for receiving an output signal of the VLC generation circuit and an output signal of the FLC generation circuit, in which in a first cycle, the first selection circuit receives a first selection signal outputted from the control circuit, selects the Level absolute value signal, and outputs the selected signal to the VLC table, the second selection circuit receives a second selection signal outputted from the control circuit, selects the Run signal, and outputs the Run signal to the VLC table, then the VLC table implements VLC and outputs an output signal to the first register, and in a second cycle, the control circuit judges whether the output signal of the first register is correct as normal VLC, and when the output signal of the first register is judged to be correct as normal VLC, outputs a third selection signal indicating the judgement result to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as a normal VLC code, and the third selection circuit selects the output signal of the VLC generation signal in accordance with the third selection signal and outputs the selected signal, and in the first cycle, the LMAX table receives the Last signal and the Run signal, generates an LMAX data signal, and outputs the generated signal to the second subtraction circuit, the second subtraction circuit receives the LMAX data signal and the Level absolute value signal, subtracts the LMAX data signal from the Level absolute value signal, and outputs an obtained result to the third register, and in the second cycle, the first selection circuit receives the first selection signal outputted from the control circuit, selects the output signal of the third register, and outputs the selected signal to the VLC table, the second selection circuit receives the second selection signal outputted from the control circuit, selects the Run signal, and outputs the Run signal to the VLC table, then the VLC table implements VLC and outputs an output signal to the first register, and in the third cycle, when the judgement of the normal VLC performed in the second cycle shows that the output signal is not correct, the control circuit judges whether the output signal of the first register is correct as LMAX VLC, and when the output signal of the first register is judged to be correct as LMAX VLC, outputs the third selection signal indicating the judgement result to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as an LMAX VLC code, and the third selection circuit selects the output signal of the VLC generation circuit in accordance with the third selection signal and outputs the selected signal, and in the first cycle, the RMAX table receives the Last signal and the Level absolute value signal, generates an PMAX data signal, and outputs the generated signal to the first subtraction circuit, the first subtraction circuit receives the RMAX data signal and the Run signal, subtracts a value that is obtained by adding the PMAX data signal and 1, from the Run signal, and outputs an obtained result to the second register, and in the third cycle, the first selection circuit receives the first selection signal outputted from the control circuit, selects the Level absolute value signal, and outputs the selected signal to the VLC table, the second selection circuit receives the second selection signal outputted from the control circuit, selects an output signal of the second register, and outputs the selected signal to the VLC table, then the VLC table implements VLC and outputs an output signal to the first register, and in a fourth cycle, when the judgement of the LMAX VLC performed in the third cycle shows that the output signal is not correct, the control circuit judges whether the output signal of the first register is correct as RMAX VLC, and when the output signal of the first register is judged to be correct as RMAX VLC, outputs the third selection signal to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as an RMAX VLC code, and the third selection circuit selects an output signal of the VLC generation circuit in accordance with the third selection signal and outputs the selected signal, and when it is judged that none of the output signals of the first register, inputted to the control circuit, is correct as VLC, in the fourth cycle, the third selection circuit selects the output signal of the FLC generation circuit and outputs the selected signal.
According to the variable length coding apparatus that is constituted as described above, the NewLevel signal and the NewRun signal can be calculated while simultaneously performing the normal VLC. In addition, although the prior art VLC process requires six cycles, this apparatus can reduce the number of process cycles to four cycles. Further, the process is conventionally carried out using three VLC tables, while this apparatus can perform the VLC with one VLC table, thereby reducing the circuit area.
According to the present invention (aspect 7), in the variable length coding apparatus of aspects 5 or 6, the control circuit judges whether the output signal of the first register is correct or not as VLC, further decides the number of cycles in which the output signal is incorrect, thereby performing control of the VLC, and changes an output order of the VLC according to predetermined priorities.
According to the variable length coding apparatus that is constituted as described above, the priorities can be arbitrarily set. Further, a unique code is always assigned in the FLC generation circuit. Therefore, when the priorities are set such that the output signal of the FLC generation circuit is selected when the normal VLC is judged and the result of the judgement is incorrect, this apparatus can conform to the image compression method according to H.263.
According to the present invention (aspect 8), there is provided a variable length coding apparatus comprising a first selection circuit for receiving a Level absolute value signal as an absolute value of a Level signal, a Last signal, and fixed values, selecting one of the Level absolute value signal and the fixed value to output a first output signal, and selecting one of the Last signal and the fixed value to output a second output signal; an RMAX table for receiving the first output signal and the second output signal; a second selection circuit for receiving a Run signal, the Last signal and fixed values, selecting one of the Run signal and the fixed value to output a third output signal, and selecting one of the Last signal and the fixed value to output a fourth selection signal; an LMAX table for receiving the third output signal and the fourth output signal; a first subtraction circuit for subtracting a sum of an output signal of the RMAX table and 1, from the Run signal; a second subtraction circuit for subtracting an output signal of the LMAX table from the Level absolute value signal; a second register for holding an output signal of the first subtraction circuit; a third register for holding an output signal of the second subtraction circuit; a third selection circuit for selecting one of an output signal of the third register and the Level absolute value signal; a fourth selection circuit for selecting one of an output signal of the second register and the Run signal; a VLC table for receiving an output signal of the third selection circuit, an output signal of the fourth selection circuit, a signal indicating the sign of the Level signal, and the Last signal; a first register for holding an output signal of the VLC table; a FLC generation circuit for receiving the Level signal, the Run signal, and the Last signal; a control circuit for receiving an output signal of the first register; a VLC generation circuit for receiving the output signal of the first register and an output signal of the control circuit; and a fifth selection circuit for receiving an output signal of the VLC generation circuit and an output signal of the FLC generation circuit, in which in a first cycle, the first selection circuit receives a first selection signal outputted from the control circuit and selects the fixed value, the second selection circuit receives a second selection signal outputted from the control circuit and selects the Run signal and the Last signal, the third selection circuit receives a third selection signal outputted from the control circuit, selects the Level absolute value signal, and outputs the selected signal to the VLC table, the fourth selection circuit receives a fourth selection signal outputted from the control circuit, selects the Run signal, and outputs the Run signal to the VLC table, and then the VLC table implements VLC and outputs an output signal to the first register, and in a second cycle, the control circuit judges whether the output signal of the first register is correct as normal VLC, and when the output signal of the first register is judged to be correct as normal VLC, outputs a fifth selection signal indicating the judgement result to the VLC generation circuit and the fifth selection circuit, the VLC generation circuit outputs the output signal of the first register as a normal VLC code, and the fifth selection circuit selects the output signal of the VLC generation circuit in accordance with the fifth selection signal and outputs the selected signal, and in the first cycle, the LMAX table receives the Last signal and the Run signal, generates an LMAX data signal, and outputs the generated signal to the second subtraction circuit, the second subtraction circuit receives the LMAX data signal and the Level absolute value signal, subtracts the LMAX data signal from the Level absolute value signal, and outputs an obtained result to the third register, and in the second cycle, the third selection circuit receives the third selection signal outputted from the control circuit, selects the output signal of the third register, and outputs the selected signal to the VLC table, the fourth selection circuit receives the fourth selection signal outputted from the control circuit, selects the Run signal, and outputs the Run signal to the VLC table, then the VLC table implements VLC and outputs an output signal to the first register, and in a third cycle, when the judgement of the normal VLC performed in the second cycle shows that the output signal is not correct, the control circuit judges whether the output signal of the first register is correct as LMAX VLC, and when the output signal of the first register is judged to be correct as LMAX VLC, outputs the fifth selection signal indicating the judgement result to the VLC generation circuit and the fifth selection circuit, the VLC generation circuit outputs the output signal of the first register as an LMAX VLC code, and the fifth selection circuit selects an output signal of the VLC generation circuit in accordance with the fifth selection signal and outputs the selected signal, and in the second cycle, the RMAX table receives the Last signal and the Level absolute value signal, generates an RMAX data signal, and outputs the generated signal to the first subtraction circuit, and the first subtraction circuit receives the RMAX data signal and the Run signal, subtracts a value that is obtained by adding the RMAX data signal and 1, from the Run signal, and outputs an obtained result to the second register, and in the third cycle, the third selection circuit receives the third selection signal outputted from the control circuit, selects the Level absolute value signal, and outputs the selected signal to the VLC table, the fourth selection circuit receives the fourth selection signal outputted from the control circuit, selects the output signal of the second register, and outputs the selected signal to the VLC table, then the VLC table implements VLC and outputs an output signal to the first register, and in a fourth cycle, when the judgement of LMAX VLC performed in the third cycle shows that the output signal is not correct, the control circuit judges whether the output signal of the first register is correct as RMAX VLC, and when the output signal of the first register is judged to be correct as RMAX VLC, outputs the fifth selection signal indicating the judgement result to the VLC generation circuit and the third selection circuit, the VLC generation circuit outputs the output signal of the first register as an RMAX VLC code, and the fifth selection circuit selects an output signal of the VLC generation circuit in accordance with the fifth selection signal and outputs the selected signal, and when it is judged that none of the output signals of the first register, inputted to the control circuit, is correct as VLC, in the fourth cycle, the fifth selection circuit selects the output signal of the FLC generation circuit and outputs the selected signal.
According to the variable length coding apparatus that is constituted as described above, the RMAX table is never accessed in the first cycle, whereby the consumed power can be reduced. Further, while the prior art VLC process requires six cycles, the number of process cycles can be reduced to four cycles. Furthermore, the processes are conventionally performed using three VLC tables, while the VLC process can be carried out with one VLC table, whereby the circuit area can be reduced.
According to the present invention (aspect 9), in the variable length coding apparatus of aspect 8, the control circuit judges whether the output signal of the first register is correct or not as VLC and further decides the number of cycles in which the output signal is incorrect, thereby performing control of the VLC, and changes an output order of the VLC according to predetermined priorities.
According to the variable length coding apparatus that is constituted as described above, the priorities can be arbitrarily set. Further, a unique code is always assigned in the FLC generation circuit. Therefore, when the priorities are set such that the output signal of the FLC generation circuit is selected when the normal VLC is judged and the result of the judgement is incorrect, this apparatus can conform to the image compression method according to H.263.